Programmable timing logic system for dual bus interface

Details Programmable timing logic system for dual bus interface Programmable timing logic system for dual bus interface

1992-10-16

1996-02-27

Auve, Glenn A.

395550, G06F 1336, G06F 1340

Patent

active

054955858

ABSTRACT:
A programmable timing logic system for enabling access to a first or second bus, of dual system busses, by a central processor and/or a protocol-timing translation logic unit wherein messages may be received from one bus while command/control data is being transmitted to the other bus. Incomplete command cycles are retried a specific number "n" of times, each for a preset predetermined time period of "p" microseconds.

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