Apparatus for evaluating the error rate of binary digital signal

Details Apparatus for evaluating the error rate of binary digital signal Apparatus for evaluating the error rate of binary digital signal

1978-04-28

1980-04-29

Griffin, Robert L.

Excavating

371 68, 371 69, H04J 314

Patent

active

042008387

ABSTRACT:
Apparatus for evaluating the error rate of a binary digital signal transmitted according to a multiple level modulation process in which a received signal is connected to a main and an auxiliary demodulator in parallel, the auxiliary modulator including means to disturb the signal, the output from the main demodulator being applied to a comparator to provide a first signal according to the comparison of a first signal pattern with a second signal pattern and the auxiliary demodulator including a comparator whose output provides a second signal according to the state of modulation of first and second received signals, the first and second signals being applied to a modulo 2 adder whose output is applied to a counter.

REFERENCES:
patent: 4064459 (1977-12-01), Markwitz
patent: 4091240 (1978-05-01), Lainey
A Bit Error Rate Monitor for Digital PSK Links, Leon et al., IEEE Transactions on Communications, vol. COM-23, #5, May, 1975.
Performance Monitor Techniques for Digital Receivers Based on Extrapolation of Error Rate, Gooding, IEEE Transactions on Communications, vol. COM-16, #3, Jun. 1968.

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