Three input arithmetic logic unit with shifter and/or mask gener

Details Three input arithmetic logic unit with shifter and/or mask gener Three input arithmetic logic unit with shifter and/or mask gener

1998-06-19

1999-11-30

Maung, Zami

Boots, shoes, and leggings

395564, 36471508, G06F 9315

Patent

active

059957484

ABSTRACT:
A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

REFERENCES:
patent: 4467444 (1984-08-01), Harmon, Jr. et al.
patent: 4785393 (1988-11-01), Chu et al.
patent: 5146592 (1992-09-01), Pfeiffer et al.
patent: 5301341 (1994-04-01), Vassiliadis et al.

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