Testing buffer/register

Details Testing buffer/register Testing buffer/register

1994-02-14

1996-02-27

Beausoliel, Jr., Robert W.

Excavating

371 226, 371 223, G01R 3128, G06F 1100

Patent

active

054954878

ABSTRACT:
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

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K. P. Parker, "Boundary Scan On Board Test", IEEE D&T of Computers, Aug. 1989 pp. 18-30.

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