High speed two's complementer

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341 93, G06F 700, H03M 700

Patent

active

054954312

ABSTRACT:
A 2's complementer having a simple circuit arrangement and yet obtaining a high 2's-complementation rate. The 2's complementer includes an inverting circuit for inverting binary data with at least two bits to produce an 1's complement. The 2's complementer also includes an inverter for inverting inverted data resulted from an inversion of the least-significant bit of the 1's-complement data of at least two bits, and at least one exclusive OR gate for comparing bit data to be currently processed with lower-order bit data of at least one bit of the 1's-complement data, and inverting the current bit data when the at least one lower-order bit data has the value of logic-1.

REFERENCES:
patent: 4520347 (1985-05-01), Campbell, Jr.
patent: 4709226 (1987-11-01), Christopher
patent: 5216424 (1993-06-01), Kouno et al.
Elliot et al. "Two's Complementor or Straight-Through Logic Arrangement", IBM Tech. Discl. Bull. vol. 12, No. 11, Apr. 1970, pp. 1978-1979.

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