Semiconductor device and method for manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

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Details

257296, 257300, 257306, 257311, 257774, H01L 2348

Patent

active

060231017

ABSTRACT:
A coverage can be improved when an upper layer is formed on an upper wiring patterned on an interlayer insulation film. A sidewall made of an insulating material is bonded to a side face of the upper wiring patterned on the interlayer insulation film. Consequently, a height difference between the upper wiring and the interlayer insulation film has a small gradient. By flattening a laminated face of the upper layers including surfaces of the upper wiring and the sidewall, a further upper layer to be formed can have a coverage improved.

REFERENCES:
patent: 5668412 (1997-09-01), Kim
patent: 5742472 (1998-04-01), Lee et al.
patent: 5796133 (1998-08-01), Kwon et al.

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