Semiconductor memory device with stacked capacitor structure and

Details Semiconductor memory device with stacked capacitor structure and Semiconductor memory device with stacked capacitor structure and

1989-05-18

1990-08-21

Griffin, Donald A.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

357 236, 437 48, H01G 406, H01L 2170, H02L 2978

Patent

active

049511750

ABSTRACT:
A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor. After a capacitor insulation layer is formed on the second polycrystalline silicon layer, a third polycrystalline silicon layer is formed on the capacitor insulation layer so as to bury a recess of the second polycrystalline silicon layer. The third silicon layer constitutes the upper electrode of the capacitor.

REFERENCES:
patent: 4271424 (1981-06-01), Inayoshi et al.
patent: 4649406 (1987-03-01), Takemae et al.
patent: 4683486 (1987-07-01), Chatterjee
patent: 4721987 (1988-01-01), Baglee et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4761385 (1988-08-01), Pfiester
patent: 4794563 (1988-12-01), Maeda

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