Static information storage and retrieval – Addressing – Sync/clocking
Patent
1999-03-04
1999-11-30
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Sync/clocking
36523002, 36523003, G11C 800
Patent
active
059954434
ABSTRACT:
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.
The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
REFERENCES:
patent: 3821715 (1974-06-01), Hoff, Jr. et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4183095 (1980-01-01), Ward
patent: 4247817 (1981-01-01), Heller
patent: 4315308 (1982-02-01), Jackson
patent: 4445204 (1984-04-01), Nishiguchi
patent: 4449207 (1984-05-01), Kung et al.
patent: 4519034 (1985-05-01), Smith et al.
patent: 4571672 (1986-02-01), Hatada et al.
patent: 4586167 (1986-04-01), Fujishima et al.
patent: 4595923 (1986-06-01), McFariand, Jr.
patent: 4646270 (1987-02-01), Voss
patent: 4649516 (1987-03-01), Chung et al.
patent: 4675850 (1987-06-01), Nakano et al.
patent: 4680738 (1987-07-01), Tam
patent: 4683555 (1987-07-01), Pinkham
patent: 4719602 (1988-01-01), Hag et al.
patent: 4734880 (1988-03-01), Collins
patent: 4757473 (1988-07-01), Kurihara et al.
patent: 4788667 (1988-11-01), Higuchi
patent: 4803621 (1989-02-01), Kelly
patent: 4821226 (1989-04-01), Christopher et al.
patent: 4845664 (1989-07-01), Aichelmann, Jr. et al.
patent: 4860198 (1989-08-01), Takenaka
patent: 4882712 (1989-11-01), Ohno et al.
patent: 4916670 (1990-04-01), Suzuki et al.
patent: 4928265 (1990-05-01), Beighe et al.
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4951251 (1990-08-01), Yamaguchi et al.
patent: 4953128 (1990-08-01), Kawai et al.
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 4954992 (1990-09-01), Kumanoya et la.
patent: 4970418 (1990-11-01), Masterson
patent: 4975872 (1990-12-01), Zaiki
patent: 5016226 (1991-05-01), Hiwada et al.
patent: 5018111 (1991-05-01), Madland
patent: 5021772 (1991-06-01), King et al.
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5083296 (1992-01-01), Hara et al.
patent: 5107465 (1992-04-01), Fung et al.
patent: 5140688 (1992-08-01), White et al.
patent: 5206833 (1993-04-01), Lee
patent: 5226009 (1993-07-01), Arimoto
patent: 5301278 (1994-04-01), Bowater et al.
patent: 5361277 (1994-11-01), Grover
patent: 5361343 (1994-11-01), Kosonocky et al.
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5745421 (1998-04-01), Pham et al.
patent: 5787041 (1998-07-01), Hill et al.
H. L. Kalter et al. "A 50-ns 16Mb DRAM with a 10-ns Data Rate and On-Chip ECC" IEEE Journal of Solid State Circuits, vol. 25 No. 5, pp. 1118-1128 (Oct. 1990).
T.L. Jeremiah et al., "Synchronous Packet Switching Memory and I/O Channel," IBM Tech. Disc. Bul,. vol. 24, No. 10, pp. 4986-4987 (Mar. 1982).
L. R. Metzeger, "A 16K CMOS PROM with Polysilicon Fusible Links", IEEE Journal of Solid State Circuits, vol. 18 No. 5, pp. 562-567 (Oct. 1983).
A. Yuen et. al., "A 32K ASIC Synchronous RAM Using a Two-Transistor Basic Cell", IEEE Journal of Solid State Circuits, vol. 24 No. 1, pp. 57-61 (Feb. 1989).
D.T. Wong et. al., "An 11-ns 8Kx18 CMOS Static RAM with 0.5-.alpha.m Devices", IEEE Journal of Solid State Circuits, vol. 23 No. 5, pp. 1095-1103 (Oct. 1988).
T. Williams et. al., "An Experimental 1-Mbit CMOS SRAM with Configurable Organization and Operation", IEEE Journal of Solid State Circuits, vol. 23 No. 5, pp. 1085-1094 (Oct. 1988).
D. Jones, "Synchronous static ram", Electronics and Wireless World, vol.93, No.1622, pp. 1243-1244 (Dec. 87).
F. Miller et. al., "High Frequency System Operation Using Synchronous SRAMS", Midcon/87 Conference Record, pp. 430-432 Chicago, IL, USA; 15-17, Sep. 1987.
K. Ohta, "A 1-Mbit DRAM with 33-MHz Serial I/O Ports", IEEE Journal of Solid State Circuits, vol. 21 No. 5, pp. 649-654 (Oct. 1986).
K. Nogami et. al., "A 9-ns HIT-Delay 32-kbyte Cache Macro for High-Speed RISC", IEEE Journal of Solid State Circuits, vol. 25 No. 1, pp. 100-108 (Feb. 1990).
F. Towler et. al., "A 128k 6.5ns Access/5ns Cycle CMOS ECL Static RAM", 1989 IEEE international Solid State Circuits Conference, (Feb. 1989).
M. Kimoto, "A 1.4ns/64kb RAM with 85ps/3680 Logic Gate Array", 1989 IEEE Custom Integrated Circuits Conference.
D. Wendell et. al. "A 3.5ns, 2Kx9 Self Timed SRAM", 1990 IEEE Symposium on VLSI Circuits (Feb. 1990).
S. Watanabe et. al., "An Experimental 16-Mbit CMOS DRAM Chip with a 100-MHz Serial Read/Write Mode", IEEE Journal of Solid State Circuits, vol. 24 No. 3, pp. 763-770 (Jun. 1982).
K. Numata et. al. "New Nibbled-Page Architecture for High Density DRAM's", IEEE Journal of Solid State Circuits, vol. 24 No. 4, pp. 900-904 (Aug. 1989).
Farmwald Michael
Horowitz Mark
Nguyen Tan T.
Rambus Inc.
Steinberg Neil A.
LandOfFree
Synchronous memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronous memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1682049