Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1998-11-10
1999-11-30
Phan, Trong
Static information storage and retrieval
Addressing
Plural blocks or banks
36518908, 36523006, G11C 800
Patent
active
059954396
ABSTRACT:
A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.
REFERENCES:
patent: 5371896 (1994-12-01), Grove et al
patent: 5566371 (1996-10-01), Ogawa
patent: 5675537 (1997-10-01), Bill et al.
IEEE JOURNAL OF SOLID STATE CIRCUIT, vol. 30, No. 9, Sep. 1995, pp. 1006-1014.
Ayukawa Kazushige
Fujita Ryo
Tanaka Hitoshi
Watanabe Takao
Yanagisawa Kazumasa
Hitachi , Ltd.
Hitachi ULSI Engineering Corporation
Nguyen Hien
Phan Trong
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