Method and circuit for the generation of programming and erasure

Details Method and circuit for the generation of programming and erasure Method and circuit for the generation of programming and erasure

1998-09-18

1999-11-30

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518519, 36518529, G11C 1604

Patent

active

059954167

ABSTRACT:
A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

REFERENCES:
patent: 5801993 (1998-09-01), Choi
patent: 5867428 (1999-02-01), Ishii et al.
Lucerno et al., "A 16 kbit Smart 5 v-Only EEPROM with Redundancy", IEEE Journal of Solid-State Circuits, vol. 18, No. 5, Oct. 1983 New York, pp. 539-544.
Gee et al., "An Enhanced 16K E2PROM", EPROM with Reduncancy IEEE Journal Of Solid-State Circuits, vol. 17, No. 5, Oct. 1982, New York--pp. 828-832.
French Search Report (Jun. 2, 1998).

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