Static information storage and retrieval – Floating gate – Particular connection
Patent
1998-07-31
1999-11-30
Phan, Trong
Static information storage and retrieval
Floating gate
Particular connection
36518518, G11C 1604
Patent
active
059954140
ABSTRACT:
A non-volatile semiconductor memory device comprises a plurality of rewritable non-volatile memory cells arranged in an array and divided into a plurality of blocks, the non-volatile memory cells of each block being connected to a bit-line block by block through a bit-line voltage converter which includes a voltage conversion circuit section and a bypass circuit section, wherein when a selection voltage for writing is applied to the bit line extending through a plurality of blocks, the selection voltage is applied as a first voltage to the bit-line within a block which has been selected for writing so as to write data into the non-volatile memory cells connected to the bit-line within the block, and is applied as a second voltage having a smaller absolute value than the first voltage to the bit-line within a block which has not been selected for writing, by means of the voltage conversion circuit section, and when a voltage for reading is applied to the bit-line extending through the plurality of blocks, the voltage is directly applied to the bit line through the bypass circuit section without using the voltage conversion circuit section. According to the present invention, it is possible to prevent drain disturb effectively and to communicate to the plurality of blocks connected to the bit-line by means of the first or second voltage that the selection voltage has been applied to the bit-line for writing.
REFERENCES:
patent: 5828621 (1998-10-01), Tanzawa et al.
patent: 5847994 (1998-12-01), Motoshima et al.
H. Onoda, et al., IEEE (1992), "A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory", pp. 599-602.
Phan Trong
Sharp Kabushiki Kaisha
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