Dynamic PLA circuit with no "virtual grounds"

Details Dynamic PLA circuit with no "virtual grounds" Dynamic PLA circuit with no "virtual grounds"

1989-09-14

1990-08-21

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307465, 307469, 307481, H03K 19177

Patent

active

049509284

ABSTRACT:
A dynamic programmable logic array circuit includes an AND logic plane (12), an inter-plane buffer (22), and an OR logic plane (14). The inter-plane buffer (22) is formed of a plurality of N-channel inter-plane FETs. Each of the plurality of N-channel inter-plane FETs has its gate electrode connected to a respective one of a plurality of product term lines and its source electrode connected to a respective one of a plurality of OR plane input lines. The drain electrodes of the plurality of inter-plane FETs are connected to receive an OR plane evaluation signal.

REFERENCES:
patent: 4467439 (1984-08-01), Rhodes
patent: 4516123 (1985-05-01), Shoji
patent: 4557190 (1986-03-01), Law
patent: 4661728 (1987-04-01), Kashimura
patent: 4740721 (1988-04-01), Chung et al.
patent: 4769562 (1988-09-01), Ghisio
patent: 4857767 (1989-08-01), Little et al.

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