Pre-charge circuit with a bipolar transistor

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307452, 307481, 307570, H03K 1901

Patent

active

049509250

ABSTRACT:
An output signal of a logic portion is inputted to the gate of FET inside an output buffer portion to inverse the signal polarity by this FET and is outputted through a bipolar transistor effecting an emitter follower operation or the like. An FET controlled by a clock signal is disposed between the base of the bipolar transistor and the ground and an FET which is turned ON during a pre-charge operation and when the bipolar transistor is OFF during logic calculation is disposed between the emitter and the ground so as to short-circuit the emitter and the ground during the pre-charge operation. In this manner, higher operation speed, higher integration density and high operation margin can be accomplished without losing the characteristic features of a Bi-CMOS dynamic logic circuit in its high operation speed and low power dissipation.

REFERENCES:
patent: 4700086 (1987-10-01), Ling et al.
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4760293 (1988-07-01), Hebenstreit
patent: 4780626 (1988-10-01), Guerin et al.
patent: 4791320 (1988-12-01), Kawata et al.
patent: 4841172 (1989-06-01), Ueno et al.

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