Array processor with parallel operations per instruction

Details Array processor with parallel operations per instruction Array processor with parallel operations per instruction

1979-09-28

1981-09-01

Smith, Jerry

Boots, shoes, and leggings

364200, G06F 928, G06F 1516, G06F 752

Patent

active

042875668

ABSTRACT:
An array processor particularly useful in performing calculations utilizing data from two distinct two-dimensional arrays. More particularly, the array processor provided by the invention incorporates multiplication, addition, subtraction, transfer and storage means whereby arithmetic and storage operations, and two-dimensional array access operations can be conducted in parallel, thereby reducing the time required for complex and cumulative vector computations which could be associated with voice digital encoding and decoding systems. An architecture scheme is described which allows parallel operations to be effected, and a simplified addressing means is disclosed for vectorally accessing locations within two two-dimensional arrays. In addition, a coding and instruction scheme is disclosed which is compatible with the disclosed architecture.

REFERENCES:
patent: 3771141 (1973-11-01), Culler
patent: 3895357 (1975-07-01), Schwartz et al.
patent: 3979728 (1976-09-01), Reddaway
patent: 4051551 (1977-09-01), Lawrie et al.
patent: 4101960 (1978-07-01), Stokes et al.

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