Process of fabricating Bi-CMOS integrated circuit device

Details Process of fabricating Bi-CMOS integrated circuit device Process of fabricating Bi-CMOS integrated circuit device

1994-06-09

1996-02-27

Fourson, George

Fishing, trapping, and vermin destroying

437192, 437193, 437200, H01L 2170, H01L 2700, H01L 2144

Patent

active

054948444

ABSTRACT:
A process of fabricating a bi-CMOS integrated circuit device has a step of selectively growing doped polysilicon over a source/drain region and a part of base region exposed to contact holes formed in a silicon oxide layer without residue of the doped polysilicon on the silicon oxide layer, thereby preventing the bi-CMOS integrated circuit device from undesirable short circuit.

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patent: 5075241 (1991-12-01), Spratt et al.
K. Nakamura et al., "A 6ns 4Mb ECL I/O BiCMOS SRAM with LV-TTL Mask Option," Reprinted from ISSCC92 Digest of Technical Papers, vol. thirty-five, Feb., 1992, 92CH3128-6, Mar. 1992, 1992 IEEE.
T. Maeda et al,. "High Performance BiCMOS Technology Design for sub-10ns 4Mbit BiCMOS SRAM with 3.3V Operation," 1992 Symposium on VLSI Technology Digest of Technical Papers, 92CH3172-4/92/0000-0032, 1992 IEEE.

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