Fishing – trapping – and vermin destroying
Patent
1993-10-13
1996-02-27
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 60, 437919, H01L 2170, H01L 2700
Patent
active
054948401
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a manufacturing method for memory cells of a DRAM (dynamic RAM).
BACKGROUND OF THE INVENTION
DRAMs having a variety of structures have been previously disclosed; they can be generally divided into stacked capacitor types, trench capacitor types, fin types, and the like. An equivalent circuit such as that used in all types is shown in FIG. 26; the capacitor is formed by means of a insulation film 40 placed between two electrodes 41 and 42, and switch 43 comprises an MOS transistor.
The accumulation charge Q in the capacitor is expressed by the following formula.
In the case in which a leak of a more or less fixed size is present in the packaged memory, if such a leak having a fixed size is permitted, it is preferable that accumulation charge Q be as large as possible. In order to increase the size of accumulated charge Q, as is clear from formulas (1) and (2), the size of dielectric constant e o may be enlarged, the opposing surface area S may be increased, or the insulation film thickness d may be reduced.
However, the recent increase in the density of DRAMs has been striking, enterring the submicron realm. When such an increase in density is carried out, the value of the opposing surface area S is reduced, and when the value of S is reduced, as can be seen from the above formulas, the capacitance C is also reduced. As a result, various methods have been attempted to increase the value of C by increasing the value of .epsilon..sub.o or of S.
However, an increase in the dielectric constant would appear from formulas (1) and (2) to lead to an increase in the accumulation charge Q; however, materials having a large dielectric constant .epsilon..sub.o have poor insulating properties, and as a result, the likelihood of charge leaks increases. An increase in .epsilon..sub.o has been carried out.
Accordingly, in order to increase the accumulation charge Q, it is not sufficient to merely increase the value of capacitance C by increasing the value of .epsilon..sub.o or the value of opposing surface area S, but rather, the insulating characteristics must be improved.
Here, to consider the conventional technology, improvements to the DRAMs having the structures described above have been attempted in order to maintain the capacitance C at a level above a specified value (40 fF or more). The trench capacitance type has the structure shown in FIG. 27, the fin type has the structure shown in FIG. 28, and the stacked capacitor type has the structure shown in FIG. 29.
In the trench capacitor type, an attempt is made to increase the opposing surface area S, and thus the capacitance, by filling a groove with an insulation film 23 and a metal film 12.
However, when the groove in a trench capacitor type becomes deep, and the aspect ratio thereof reaches a level of 20-30, the cleaning of the interior of the groove becomes difficult, and film deposition may be conducted on the contaminated surface. Furthermore, insulation breakdown occurs easily in the corner areas of the groove, so that the reliability and yield thereof are extremely poor.
The fin type is employed in order to increase the opposing surface area by means of the multilayering of metal film 12, and in order to thus increase the capacitance. However, it is also difficult to conduct cleaning in the interior of the very detailed structure of the fin type, and furthermore, defects in resistance to insulation breakdown occur easily at edge areas thereof.
On the other hand, the stacked capacitor type is easier to manufacture than the trench capacitor type or the fin type, and furthermore, has superior reliability and yield.
Conventionally, a stacked capacitor type was produced in the following manner. To explain based on FIGS. 30 and 31, the surface of an N.sup.+ region 7 which was covered by an insulation film 3 was exposed by means of an RIE method (reactive ion etching), or the like, and a conductive film 12 was formed thereon by means of depositting polysilicon; after this, a resist 15 was formed with a desi
REFERENCES:
patent: 4002545 (1977-01-01), Fehiner
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 4495219 (1985-01-01), Kato
patent: 5142438 (1992-08-01), Reinberg et al.
patent: 5217914 (1993-06-01), Matsumoto et al.
Chaudhuri Olik
Tsai H. Jey
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