Error checking and correcting device

Details Error checking and correcting device Error checking and correcting device

1976-06-14

1978-02-28

Atkinson, Charles E.

Communications: electrical

Digital comparator systems

G06F 1112

Patent

active

040770281

ABSTRACT:
An error checking and correcting device for providing group error detection in addition to single error correction and double error detection in a codeword transmitted through a modular communication channel is disclosed. The codeword comprises a plurality of data bits and a plurality of check bits. The modular communication channel comprises a plurality of modules in each of which a group (or cluster) of bits are transferred in parallel. In the preferred embodiment, the code word contains 40 bits with 32 data bits and 8 check bits, and the modular communication channel is a computer memory comprising 10 modules with 4 bits per module. At the transmitter, the check bit generator generates the check bits from the data bits in accordance with an H-matrix which is partitioned into h-submatrices corresponding to group boundaries of the memory. The construction of the h-submatrices is in accordance with rules necessary for group error detection in addition to single error correction and double error detection. The check bits are appended to the data bits to form a 40 bit code word which is transmitted through the modular memory. At the receiver, a syndrome bit generator generates 8 syndrome bits from the received code word in accordance with the H-matrix. The output of the syndrome bit generator is coupled to both the error detection circuit and the error location circuit. Should a group in the memory be faulty in the process of transmission resulting in a number of bits in the group being in error, logic means are provided in the error detection circuit to identify correctable good data from uncorrectable bad data. According to the syndrome pattern the error detection circuit permits the utilization of received data if no error is detected, or enables the error location circuit to provide single error correction if a single error is detected; or sets an error flag to prohibit the utilization of received data if a random double error is detected or a plurality of errors in the same group are detected.

REFERENCES:
patent: 3697948 (1972-10-01), Bossen
patent: 3745525 (1973-07-01), Hong et al.
patent: 3745526 (1973-07-01), Hong et al.

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