Processing circuit capable of raising throughput of accumulation

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364736, 364754, G06F 738, G06F 752

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active

048112682

ABSTRACT:
In a processing circuit for successively accumulating a first predetermined number of products, each product is shifted in a barrel shifter (20) downwards by a second predetermined number of bits determined in relation to the first predetermined number and is successively added to a previous result of accumulation in an arithmetic/logic unit (ALU) (21) the first predetermined number of times to produce a final result of accumulation. The first result is shifted in a shifter (27) upwards by a third predetermined number of bits determined in relation to the second predetermined number. An overflow detector (26) monitors each result of accumulation to detect occurrence of an overflow in the ALU and the shifter to substitute either a positive or a negative maximum number for each result by an overflow corrector (25) on occurrence of the overflow. The substituted maximum number or the shifted final result is produced as an output signal.

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Nishitani et al., "A Single-Chip Digital Signal Processor for Telecommunication Applications", IEEE Journal of Solid State Circuits, vol. SC-16, No. 4 (Aug. 1981), pp. 372-376.
Erskine, et al., "Architecture and Applications of a Second-Generation Digital Signal Processor", Proceedings ICASSP 85, IEEE Int'l Conf. on Acoustics . . . , vol. 1, pp. 228-231.
The Bipolar Digital Integrated Circuits Data Book, Texas Instruments, Inc., 1985, pp. 7-234 to 7-239.
Schottky and Lowpower Schottky Data Book Including Digital Signal Processing Handbook, Advanced Micro Devices, Inc., 1977, pp. 4-37 to 4-46.

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