Distributed arithmetic realization of second-order normal-form d

Details Distributed arithmetic realization of second-order normal-form d Distributed arithmetic realization of second-order normal-form d

1986-09-19

1989-03-07

Harkcom, Gary V.

Boots, shoes, and leggings

G26F 738

Patent

active

048112623

ABSTRACT:
A high-speed distributed-arithmetic realization of a second-order normal-form digital filter includes a filter input, a filter output, and a memory. The memory has a first input, a second input, and a third input. The first memory input is connected to the filter input. The memory also has a first output, a second output, and a third output. The digital filter additionally includes a first adder having an input connected to the first memory output, and having its output connected to the filter output. A second adder has an input connected to the second memory output, and has its output connected to the second memory input. A third adder has an input connected to the third memory output and has its output connected to the third memory input.

REFERENCES:
patent: 4450533 (1984-05-01), Petit et al.
patent: 4454590 (1984-06-01), Belt et al.
patent: 4521866 (1985-06-01), Petit et al.
Peled and Liu, Digital Signal Processing: Theory, Design, and Implementation, pp. 212-260, 1976.
Barnes, Casper W., "A Parametric Approach to the Realization of Second-Order Digital Filter Sections," IEEE Transactions of Circuits & Systems, vol. CAS-32, No. 6, Jun. 1985.
Tran, Boi N., "Cad Approach to Realize a Second-Order Digital Filter Sections" (unpublished), dated 2/12/86.
Tran, Boi N., "A Preliminary Study of Architectures for a State-Space Digital Filter" (unpublished), dated 2/12/86.

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