Cache memory with multiple valid bits for each data indication t

Details Cache memory with multiple valid bits for each data indication t Cache memory with multiple valid bits for each data indication t

1986-07-31

1989-03-07

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1208

Patent

active

048112097

ABSTRACT:
Each entry in a cache memory located between a processor and an MMU has two valid bits. One valid bit is associated with the user execution space and the other with the supervisor or operating system execution space. Each collection of valid bits can be cleared in unison independently of the other. This allows supervisor entries in the cache to survive context changes without being purged along with the user entries.

REFERENCES:
patent: 4504902 (1985-03-01), Gallaher et al.
patent: 4525778 (1985-06-01), Cane
patent: 4602368 (1986-07-01), Circello et al.
patent: 4612612 (1986-09-01), Woffinden et al.
patent: 4638454 (1987-01-01), Waterworth
patent: 4654819 (1987-03-01), Stiffler et al.
Lin-"Fast Purging for an Array Table", IBM TDB, vol. 23, No. 3, Aug. 1980, pp. 1128-1133.

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