Interlace inversion corrector for a picture-in-picture video sig

Details Interlace inversion corrector for a picture-in-picture video sig Interlace inversion corrector for a picture-in-picture video sig

1987-03-30

1989-03-07

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 22, H04N 5262, H04N 5272

Patent

active

048111031

ABSTRACT:
A picture-in-picture video signal generator includes a source of an auxiliary video signal, and a producer of successive samples representing the auxiliary video signal. A self-sequencing memory includes a data input terminal coupled to the producer of auxiliary video samples; a write address input terminal, for receiving an initial write address; a data output terminal and a read address input terminal for receiving an initial read address. Write control circuitry is coupled to the write address terminal of the self-sequencing memory, and generates initial write addresses in synchronism with horizontal line intervals of the auxiliary video signal. A source of a main video signal is also provided. An interlace inversion detector is coupled to the main and auxiliary video signal sources and produces an inversion detect signal indicating that an interlace inversion condition has been detected. Read control circuitry is coupled to the read address terminal of the self-sequencing memory, and generates initial read addresses in synchronism with horizontal line intervals of the main video signal and generates a modified sequence of initial read addresses in response to the inversion detect signal. The main video signal is combined with samples from the self-sequencing memory to form a video signal representing a picture-in-picture image.

REFERENCES:
patent: 4249213 (1981-02-01), Imaide et al.
patent: 4267560 (1981-05-01), Ishikawa et al.
patent: 4656515 (1987-04-01), Christopher
patent: 4724487 (1988-02-01), Casey
"LM1881 Video Sync Separator"; National Semiconductor; Apr. 1986.

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