Image analysis – Image transformation or preprocessing – Multilayered image transformations
Patent
1992-06-01
1997-08-12
Boudreau, Leo
Image analysis
Image transformation or preprocessing
Multilayered image transformations
382303, 382304, 382308, G06K 954, G06K 960
Patent
active
056574037
ABSTRACT:
A coprocessor in an image processing system is coupled to the bus to which a CPU and RAM holding image data are also coupled. The coprocessor extracts an input pixel stream corresponding to input images from selected bus transactions, performs computations on the input stream to produce output pixel streams corresponding to output images, and inserts the output pixel streams into selected CPU-to-memory bus transactions so that the memory stores the data. The CPU generates the selected bus transactions with specially marked address and/or control signals. The coprocessor includes a lookup table, and a first row delay. The row delay accumulates the three most recent rows of input pixels, which are sent to Sobel and rank processing sections for neighborhood processing. The results are thresholded and formatted, and are either output directly or passed through an additional pair of row delays to accumulate three rows of result data for neighborhood peak detection.
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patent: 5046190 (1991-09-01), Daniel et al.
patent: 5253308 (1993-10-01), Johnson
Bursky, "CMOS Four-Chip Set Processes Images at 20-MHz Data Rates", Electronic Design, May 28, 1987, pp. 39-44.
Plessey Semiconductors, Preliminary Information, May 1986, Publication No. PS 206.
Rosenthal Steven Mark
Schott Jean-Pierre
Silver William Michael
Wolff Robert Anthony
Boudreau Leo
Cognex Corporation
Powsner David J.
Tran Phuoc
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