Data processor including a decoding unit for decomposing a multi

Details Data processor including a decoding unit for decomposing a multi Data processor including a decoding unit for decomposing a multi

1995-05-01

1996-07-30

Treat, William M.

Boots, shoes, and leggings

364DIG1, G06F 930

Patent

active

055420605

ABSTRACT:
A data processor, comprises: an instruction decoding unit which decomposes both the instruction for loading plural data onto registers from a memory, and the instruction for storing plural data into the memory from the registers into plural internal codes; an instruction executing unit which is connected with an external memory through a data bus and executes the instruction; and an instruction execution control unit which controls execution of the instruction by the instruction executing unit, in accordance with respective internal codes outputted from the instruction decoding unit, and is capable of processing the instruction for loading plural data onto the register from the memory or storing into the memory from the register by one instruction at high efficiency, by executing decoding processing of the instruction decoding unit for outputting the internal codes, and instruction execution of the instruction executing unit in accordance with the internal codes outputted in an overlapping fashion with each other in accordance with the principle of pipelining.

REFERENCES:
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4977497 (1990-12-01), Sakamura et al.
patent: 5201039 (1993-04-01), Sakamura
"Computer Architecture A. Quantitative Approach", Hennessy et al, Morgan Kaufmann Publisher's Inc. 1990, pp. 208-215.

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