Shift register for refreshing a MIS dynamic memory

Details Shift register for refreshing a MIS dynamic memory Shift register for refreshing a MIS dynamic memory

1984-09-10

1987-07-07

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

307480, 307571, 307482, 307578, G11C 1928

Patent

active

046792147

ABSTRACT:
A shift register having a simple circuit structure and used, for example, in a dynamic RAM device for a refresh operation. The shift register includes a plurality of circuit stages mutually connected in cascade. Each of the circuit stages includes a first transistor, for a transfer gate, which is turned on and off by a first clock signal and to which is input the output signal of the previous circuit stage. A second transistor is provided whose gate electrode is connected to the output of the first transistor, whose drain or source electrode receives a second clock signal having a different phase from the first clock signal, and whose source or drain electrode outputs an output signal. Each circuit stage also includes a reset circuit for rendering the input portion of the first transistor to a reset condition on the basis of the output signal, thereby sequentially transmitting data through each circuit stage.

REFERENCES:
patent: 3601637 (1971-08-01), Spence
patent: 3683203 (1972-08-01), Smith
patent: 4295055 (1981-10-01), Takemoto et al.
patent: 4341960 (1982-07-01), Naiff
"A 4096-b One Transistor Per Bit Random-Access Memory with Internal Timing and Low Dissipation", by Loek Boonstra et al., IEEE Journal of Solid-State Circuits, vol. 8, SC-8, No. 5, Oct. 1973.

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