Semiconductor memory device with a bit error detecting function

Details Semiconductor memory device with a bit error detecting function Semiconductor memory device with a bit error detecting function

Filed on

1985-02-26

Date issued

1987-07-07

Examiner

Smith, Jerry

Patent Class

Excavating

Other Related Categories

371 50, 364200, 364900, G06F 1110

Type

Patent

Status

active

Patent number

046791965

Description

ABSTRACT:
A memory matrix array consists of a plurality of memory cells with addresses expressed by a plurality of bits. The parity bit for the data stored in all of the memory cells of each linear memory cell array in the row direction are stored in the corresponding one of a plurality of parity storage cells. Storage is made into second and third parity storage cells, respectively, the parity bits for the data stored in all of the memory cells which are specified such that the corresponding bits of the addresses of the memory cells in the memory matrix array are high in logical level. In a read mode, the parity is read out from the first to third parity storage cells of the parity memory circuit.

REFERENCES:
patent: 3599146 (1971-08-01), Weisbecker
patent: 3806716 (1974-04-01), Lahti
patent: 4355393 (1982-10-01), Kubo
patent: 4365332 (1982-12-01), Rice
patent: 4371963 (1983-02-01), Edwards
patent: 4453251 (1984-01-01), Osman
patent: 4456980 (1984-06-01), Yamada
patent: 4464755 (1984-08-01), Stewart
Tsuneo Mano, et al., "Submicron VLSI Memory Circuits," IEEE International Solid-State Circuits Conference, ISSCC, 2/25/83.
Osman, "Error-Correcting Technique for Random-Access Memories," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, 10/82.

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