Drive circuit for character and graphic display device

Details Drive circuit for character and graphic display device Drive circuit for character and graphic display device

1980-06-10

1983-06-14

Curtis, Marshall M.

Communications: electrical

Continuously variable indicating

With meter reading

340798, 340750, G09G 100

Patent

active

043886213

ABSTRACT:
In a .phi..sub.2 cycle steal mode, a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator for display is extended and a time period during which the RAM is connected to a CPU is shortened accordingly, without changing an overall period. This clock signal is used to actuate a switching circuit for the RAM while a clock signal having unmodified duty ratio is applied to the CPU, a ROM and external circuits so that a display data readout period from the RAM is extended without affecting the CPU clock frequency and the operation of other circuits. During this readout period, a plurality of display address signals are applied to the RAM from the timing signal generator and a plurality of data derived from the RAM are sequentially loaded in a register which is then read out at a desired timing to enable the display of a plurality of characters in one CPU clock period.

REFERENCES:
patent: 3585677 (1971-06-01), Christopher
patent: 3771155 (1973-11-01), Hayashi et al.

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