Method of operating a data processing system in response to an i

Details Method of operating a data processing system in response to an i Method of operating a data processing system in response to an i

1986-06-24

1989-03-28

Eng, David Y.

Boots, shoes, and leggings

G06F 940

Patent

active

048169927

ABSTRACT:
A data processing system has a main memory unit (MMU) and an execution processing unit (EPU). The performance of the EPU is enhanced during interrupt processing by providing a basic processor status (BPS) storage and an extended processor status (EPS) storage. The status of the EPU is divided into the BPS and EPS, the BPS containing the contents of a general register that are frequently stored during interrupt processing, and the EPS containing the contents of registers infrequency stored during interrupt processing. The status of the EPU can be saved at any desired address location of the MMU designated by current and new processor status block (PSB) pointers that can be programmably altered. In addition, the address designated by the current and new PSB pointers can be set as logical or absolute addresses.

REFERENCES:
patent: 3789365 (1974-01-01), Jen et al.
patent: 4228495 (1980-10-01), Burnhard et al.
"IBM System/370 Extended Architecture-Principles of Operation", Chapter 2-Organization, Chapter 3-Storage, and Chapter 6-Interruptions, Mar. 1983, pp. 2-1 to 2-3, 3-37, to 3-44, and 6-1 to 6-8.
"NEC System 1000 General Description", Chapter 2, NEC Corporation, 1982, pp. 2-12 to 2-13, 2-35 to 2-42.

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