High density vertical trench transistor and capacitor memory cel

Details High density vertical trench transistor and capacitor memory cel High density vertical trench transistor and capacitor memory cel

1987-07-20

1989-03-28

James, Andrew J.

357 55, 357 41, H01L 2978, H01L 2906, H01L 2702

Patent

active

048168840

ABSTRACT:
A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate and an epitaxial layer disposed thereon. A relatively deep polysilicon filled trench is disposed in the epitaxial layer and substrate structure, the deep trench having a composite oxide
itride insulation layer over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer over the deep trench region, the shallow trench having an oxide insulation layer on its vertical and horizontal surfaces thereof. A neck structure of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer on either side of the shallow trench to form semiconductor device drain junctions and polysilicon material is disposed in the shallow trench and over the epitaxial layer to form semiconductor device transfer gate and wordline regions respectively.

REFERENCES:
IBM Technical Disclosure Bulletin, vol. 27, No. 12, May 1985, Dynamic RAM Cell Structure, p. 7051.
IBM Technical Disclosure Bulletin, vol. 29, No. 5, Oct. 1986, High Density Verical DRAM Cell, p. 2335.
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, Dynamic RAM Cell with Merged Drain and Storage, p. 6694.

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