Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1987-10-09
1989-03-28
Zazworsky, John
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307359, 307546, 307562, 307264, H03K 508
Patent
active
048166995
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a slice amplifier using filed effect transistors (FETs).
A slice amplifier plays an important role as an element of a very high speed data transmission system. For example, the slice amplifier is mounted in a data discrimination unit at a transmitter side or a receiver side of a pulse code modulation (PCM) optical communication system. The data discrimination unit contains, for examples, a D-flip flop (FF) which produces logic "1" and "0" composing a base band data. At the D-FF, an input signal given to the D input terminal thereof, is sampled by a clock signal given to the C-input terminal thereof. In this case, if a phase deviation occurs in the input signal, it is difficult to correctly sample the input signal with a predetermined timing, and therefore, a data error will occur. Accordingly, the input signal is first sliced at a certain constant level, and then the peak-to-peak level is enlarged to Obtain a rectangular-shaped waveform. In this case, the input signal can be discriminated to obtain correct data, even though a phase deviation has more or less occurred in the input signal. This is the function of the slice amplifier, which can be employed in a wave reshaping circuit.
BACKGROUND ART
FIG. 1 is a schematic diagram of a conventional data discrimination unit including a slice amplifier. In FIG. 1, an input signal S.sub.in is first received by a slice amplifier 11. The slice amplifier 11 constitutes, together with a wave reshaping part 12 following the amplifier 11, a data discrimination unit 10. The input signal S.sub.in is an analog signal having the waveforms as shown, and each waveform represents a data logic "0" or "1". Although the waveforms have already passed through an equalizer (not shown), each waveform still has a peak shape. Whether each mountain-shaped waveform represents a data logic "0" or "1" is determined by a waveform reshaping part 12, which is comprised of a D-flip flop (FF) for sampling each waveform by using a constant clock CLK. In this case, of course, the inherent digital output data D.sub.out can be reproduced if the waveform is correctly sampled by the clock CLK. If, however, the phase deviation occurs in the clock CLK, the clock timing cannot be aligned with the top of each peak of the waveform, and therefore, the clock samples the valley portion between the two adjacent peak waveforms, and thus a discrimination error is produced.
To overcome the problem of phase deviation, the waveform of the input signal S.sub.in is sliced at a certain level, for example, a level TH, and the thus-sliced signal is then transformed into a rectangular-shaped waveform signal which is an output signal S.sub.out. Therefore, the data logic "1" can be correctly sampled even if there is a more or less phase deviation of the clock. Namely, the slice amplifier 11 achieves the aforesaid transformation of the signal, i.e., S.sub.in .fwdarw.S.sub.out.
FIG. 2 is a circuit diagram illustrating an example of a prior art slice amplifier. The prior art slice amplifier 11 is comprised of a first bipolar transistor Q.sub.1 receiving the input signal S.sub.in at its base, a second bipolar transistor Q.sub.2 receiving a reference voltage V.sub.ref at its base, and producing the output signal S.sub.out, and a constant current source CS, and thus forms, as a whole, a current switch.
The prior art slice amplifier of the bipolar transistor type shown in FIG. 2 can not cope with very high speed data transmission because, due to the operation limit of the bipolar transistor per se, the slice amplifier is limited to a data transmission maximum speed on the order of 500 Mb/s.
The present invention is based on the employment of a field effect transistor (FET), instead of the bipolar transistor, to abolish this operation limit. For example, a GaAs.multidot.FET or a high electron mobility transistor, so-called HEMT, can raise the operation limit up to the order of several G b/s. In view of this, the inventors have attempted to replace the bipolar transistors Q.sub.
REFERENCES:
patent: 4162412 (1979-07-01), Mawhinney et al.
Miyaki Yuji
Mori Masakazu
Ohkuma Yoshinori
Suzuki Kazuhiro
Wada Tetsuo
Fujitsu Limited
Zazworsky John
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