Load buffer integrated dynamic decoding logic

Details Load buffer integrated dynamic decoding logic Load buffer integrated dynamic decoding logic

1995-12-29

1998-07-21

Donaghue, Larry D.

395376, 395392, G06F 1208

Patent

active

057846391

ABSTRACT:
A novel method to quickly decode a block-code in a load buffer and compare it against multiple wake-up signals in an out-of-order processor. A block-code is used to describe the blocking condition that prevents a load operation from being dispatched. Each wake-up signal indicates that the blocking conditions corresponding to certain block codes have been resolved. For each entry in the load buffer, a dynamic decoder decodes the block-code and a compare logic determines if the wake-up signal corresponding to the block-code is active. If the wake-up signal corresponding to the block-code is active, the load entry is marked ready for dispatch. Since, the blocking conditions may change each clock cycle, the decode and compare should be done each clock cycle to achieve optimal performance. Faster decode and compare may permit higher clock frequencies if the processor is limited by the decode and compare.

REFERENCES:
patent: 5191649 (1993-03-01), Cadambi et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5280615 (1994-01-01), Church et al.
patent: 5420990 (1995-05-01), McKeen et al.
patent: 5420991 (1995-05-01), Konigsfeld et al.
patent: 5467473 (1995-11-01), Kahle et al.
patent: 5481679 (1996-01-01), Higaki et al.
patent: 5588126 (1996-12-01), Abramson et al.
patent: 5606670 (1997-02-01), Abramson et al.
patent: 5625835 (1997-04-01), Ebcioglu et al.
patent: 5664137 (1997-09-01), Abramson et al.
patent: 5666506 (1997-09-01), Hesson et al.
patent: 5694574 (1997-12-01), Abramson
Johnson, Mike;Superscalar Microprocessor Design; Prentice Hall, Inc., New Jersey, 1991.
Popescu, Val; Schultz, Merle; Spracklen, John; Gibson, Gary; Lightner, Bruce; Isaman, David, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. Nos. 10-13 and 63-73.

Affiliated with

Also associated with

Rating

Load buffer integrated dynamic decoding logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Load buffer integrated dynamic decoding logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Load buffer integrated dynamic decoding logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1657790