Data processing system having memory controller for supplying cu

Details Data processing system having memory controller for supplying cu Data processing system having memory controller for supplying cu

1996-10-28

1998-07-21

Meky, Moustafa M.

G06F 1502

Patent

active

057845824

ABSTRACT:
A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.

REFERENCES:
patent: 4755938 (1988-07-01), Tukahashi et al.
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5416739 (1995-05-01), Wong
patent: 5600605 (1997-02-01), Schaefer
patent: 5602781 (1997-02-01), Isobe
patent: 5630096 (1997-05-01), Zuravleff et al.
patent: 5638534 (1997-06-01), Mote, Jr.
patent: 5655105 (1997-08-01), McLaury

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