Fault detection circuit capable of detecting burst errors in an

Details Fault detection circuit capable of detecting burst errors in an Fault detection circuit capable of detecting burst errors in an

1988-04-14

1990-03-27

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

049127128

ABSTRACT:
A fault detection circuit comprises an LRU memory having a series of bit storage cells for storing data bits therein, the stored bits indicating relationships between most recently referenced timings for each of address levels. Updating input data bits are generated by an LRU updated logic in response to the LRU memory being accessed from an external source and applying the generated updating input data bits to the LRU memory to cause same to generate updated output data bits. One of the updating input data bits is inverted prior to application to the LRU memory. An error detection circuit is responsive to the updated output data bits for detecting an error therein. One of the updated output data bits corresponding in binary significant position to the inverted updating input data bit is inverted prior to application to the error detection circuit. The inversion processes at the input and output of the LRU memory allow error-free data bits to be unaffected and the inversion process at the output of the memory causes a string of all zero's or all one's therein to be converted to a pattern which can be detected as an illegal by the error detection circuit.

REFERENCES:
patent: 4322795 (1982-03-01), Lange et al.
patent: 4334289 (1982-06-01), Lange et al.
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4761733 (1988-08-01), McCrocklin et al.

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