Multiplex communications – Wide area network – Packet switching
Patent
1988-11-01
1990-03-27
Orsino, Joseph A.
Multiplex communications
Wide area network
Packet switching
H04Q 1104
Patent
active
049127004
ABSTRACT:
In order to permit multislot connections to be simply made across a telecommunications digital switch, so that all the slots of the multislot connection experience the same whole frame time delay, the switch is constructed as input and output switch stages each comprising arrays of digital switching modules (DSM) and a central switching area comprising two arrays of Demultiplexing/Mixing/Remultiplexing devices (DMR) interconnected by an array of digital switching modules (DSM), wherein each DMR has a transfer function such that a channel (p) in a time frame of (q) channels on an input line (r) appears on an output line (s) which is related to the input line by means of a backward rotate function, where s=MOD (q-r+p), where MOD=modulo q. This construction of switch ensures that all channels routed through the switch have one of only two possible values of whole frame time delay, thereby simplifying the setting up of a multislot connection.
REFERENCES:
patent: 4400627 (1983-06-01), Zola
patent: 4566094 (1986-01-01), Ardon et al.
IEE Conference Proceedings, Pub. No. 300; IEE Second National Telecommunications Conference; York, England; Apr. 2-5 89, pp. 321-326.
GEC Plessey Telecomm. Ltd.; "Analysis of Multi-Slot Connections", T. S. Maddern, Slides 1-17.
Chopping Geoffrey
Maddern Thomas S.
Orsino Joseph A.
Scutch III Frank M.
The Plessey Company PLC
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