Parallel surface processing system for graphics display

Details Parallel surface processing system for graphics display Parallel surface processing system for graphics display

1987-10-30

1990-03-27

Clark, David L.

Boots, shoes, and leggings

364522, 340747, G06F 1572

Patent

active

049126598

ABSTRACT:
A Pipeline and Parallel Processing system for generating Surface Patches for both Wireframe and Solid/Shaded Models in a Raster Graphics Display. The inputs to a Transformation Processor are the parameters for the Rational Bezier Surfaces: a 2-dimensional array of control points, and weights. The outputs are the coordinates of the corner points and the normals (to the surface) of the patches, which make up the surface. The system consists of three Pipeline stages: (1) A front-end processor fetches the data from memory and feeds the Transformation Processor; (2) four Floating Point Processors in Parallel for tessellating the surfaces into small patches; and (3) one Floating Point Processor for generating normals at the vertices of the small patches. The output is sent to the rest of the Graphics System for clipping, mapping, and shading.

REFERENCES:
patent: 4630234 (1986-12-01), Holly
patent: 4646251 (1987-02-01), Hayes et al.
patent: 4658247 (1987-04-01), Gharachaloo
patent: 4737921 (1988-04-01), Goldwasser et al.
patent: 4752828 (1988-06-01), Chapuis et al.
patent: 4791581 (1988-12-01), Ohba
patent: 4819192 (1989-04-01), Kuragano et al.

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