Trench type semiconductor memory device having side wall contact

Details Trench type semiconductor memory device having side wall contact Trench type semiconductor memory device having side wall contact

1988-08-08

1990-03-27

Hille, Rolf

357 55, 357 41, H01L 2978, H01L 2906, H01L 2702

Patent

active

049125354

ABSTRACT:
A semiconductor substrate is formed on its major surface with a first trench and a second trench which is deeper than the first trench. A region held between the first and second trenches serves as a transistor, and impurity regions for serving as source/drain regions are formed on the first and second trench sides. A bit line fills up the first trench and a capacitor electrode fills up the second trench, to be in contact with the impurity regions respectively. A word line is formed on a channel region between the source and drain regions through an oxide film. A semiconductor layer is formed on the major surface of a semiconductor substrate through an oxide film, to be provided with a first trench having the oxide film as a bottom surface and a second trench reaching the semiconductor substrate. The semiconductor layer held between the first and second trenches serves as a transistor, while a bit line and a capacitor electrode fill up the first and second trenches respectively. Two trenches are formed on the major surface of a semiconductor substrate to be provided with a semiconductor device, so that the trenches are filled up with interconnection members. The trenches are respectively provided on their side walls with impurity regions, which are connected with each other by an impurity region formed on the major surface of the semiconductor substrate.

REFERENCES:
patent: Re32090 (1986-03-01), Jaccodine et al.
patent: 4503451 (1985-03-01), Lund et al.
patent: 4801988 (1989-01-01), Kenney
patent: 4801989 (1989-01-01), Taguchi
patent: 4820652 (1989-04-01), Hayashi
M. Taguchi et al., "Dielectrically Encapsulated Trench Capacitor Cell", IEDM 86 (1986): 136-139.
K. Fujishima et al., "A 256K Dynamic RAM with Page-Nibble Mode" IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, (Oct., 1983): 470-478.
F. Baba et al., "A 64K DRAM with 35 ns Static Column Operation", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, (Oct. 1983): 447-451.
S. Nakajima et al., "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM", IEDM 84, (1984): 240-243.

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