Parity checking circuitry for use in multi-bit cell PCM recordin

Details Parity checking circuitry for use in multi-bit cell PCM recordin Parity checking circuitry for use in multi-bit cell PCM recordin

1980-02-01

1982-03-23

Atkinson, Charles E.

Excavating

371 37, G06F 1110

Patent

active

043217044

ABSTRACT:
A method and apparatus for detecting errors in the accuracy of multi-bit data words, i.e., a parity method and apparatus, is disclosed. The invention is intended for use in determining the accuracy of multi-bit data words that are being transmitted through a communication channel or are being recorded and reproduced using magnetic recording or other technique. One embodiment of the invention involves examining at least three significant bits in at least three successive words and generating parity bits with predetermined logical states determined by the content of the examined significant bits and combining one of the parity bits with each of the data words for transmission or recording and subsequently examining the data words and parity bits upon receipt and generating an error signal for the data words when one of the parity bits combined with the examined data words has a logical state other than that that would have been transmitted or recorded if determined by the original content of the received data words.

REFERENCES:
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patent: 3387261 (1968-06-01), Betz
patent: 3601798 (1971-08-01), Hsiao
patent: 3634821 (1972-01-01), Bossen et al.
patent: 3831144 (1974-08-01), En
patent: 3876978 (1975-04-01), Bossen et al.
patent: 4016409 (1977-04-01), Kim
patent: 4044328 (1977-08-01), Herff
patent: 4211997 (1980-07-01), Rudnick et al.

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