Logic cell array using CMOS EPROM cells having reduced chip surf

Details Logic cell array using CMOS EPROM cells having reduced chip surf Logic cell array using CMOS EPROM cells having reduced chip surf

1990-02-26

1991-05-14

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365181, 36518908, 307465, G11C 1134

Patent

active

050162179

ABSTRACT:
An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.

REFERENCES:
patent: 4175290 (1979-11-01), Harari
patent: 4228527 (1980-10-01), Gerber et al.
patent: 4596938 (1986-06-01), Cartwright, Jr.
patent: 4686558 (1987-08-01), Adam

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