Prediction of number of data words transferred and the cycle at

Details Prediction of number of data words transferred and the cycle at Prediction of number of data words transferred and the cycle at

1979-01-02

1982-03-23

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 934

Patent

active

043216684

ABSTRACT:
A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digits from the operand into words containing a maximum of 8 decimal digits for transfer to the execution unit. The execution unit processes the words in accordance with a decimal numeric instruction. The throughput of the system is increased when processing short operands which contain 15 decimal digits or less by apparatus in the decimal unit which detects the short operand and determines the number of cache memory cycles between the cycle the first word of the short operand is received from cache memory and the cycle on which the first assembled word is transferred to the execution unit for processing.

REFERENCES:
patent: 3292158 (1966-12-01), Schneberger
patent: 3766532 (1973-10-01), Liebel, Jr.
patent: 4023023 (1977-05-01), Bourrez et al.
patent: 4151593 (1979-04-01), Jenkins et al.

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