Stacked CMOS sRAM with vertical transistors and cross-coupled ca

Details Stacked CMOS sRAM with vertical transistors and cross-coupled ca Stacked CMOS sRAM with vertical transistors and cross-coupled ca

1990-07-05

1991-05-14

James, Andrew J.

357 234, 357 237, 357 41, 357 42, 357 49, 357 54, 357 55, 357 59, H01L 2968, H01L 2910, H01L 2701

Patent

active

050160702

ABSTRACT:
A transistor cell (80) and enabling transistor (118) are provided. The transistor cell includes a trench transistor and a stacked transistor, with a cross-coupled capacitor between the gates of these transistors. The trench transistor includes a semiconductor region (98) functioning as a gate and first and second diffused regions (126, 135) as the source/drain regions therefor. The stacked transistor has a semiconductor layer (104) functioning as the gate and first and second doped regions (112, 114) within a semiconductor layer (110) functioning as the source/drain regions therefor. The stacked capacitor included herewith comprises semiconductor layer (104) and semiconductor region (98) having insulating layers (96, 102) therebetween.

REFERENCES:
patent: 4243997 (1981-01-01), Natori et al.
patent: 4453305 (1984-06-01), Janes et al.
patent: 4724530 (1988-02-01), Dingwall
patent: 4771323 (1988-09-01), Sasaki
patent: 4794561 (1988-12-01), Hsu

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