Large-scale EPROM memory

Details Large-scale EPROM memory Large-scale EPROM memory

1989-08-11

1991-05-14

James, Andrew J.

357 236, 357 2311, 357 53, H01L 2968

Patent

active

050160699

ABSTRACT:
An electrically programmable non-volatile memory comprises floating gate MOS transistors (T11, T12, T13) and an array of word lines (LM1 and LM2) along rows and bit lines (LB1, LB2 and LB3) along columns. A constant-potential line (B), arranged along a column so it is positioned between a pair of bit lines, connects the source electrodes (22) of the transistors, and includes a first conductivity type diffusion. A drain electrode (21) of the first conductivity type of each transistor extends along a column to form one of the bit lines (LB1, LB2, LB3). An insulating area (24) extends along a column on the side of each bit line opposite a constant-potential line (B). A conductive area (E) corresponding to the floating gate level covers insulating area (24).

REFERENCES:
patent: 4360900 (1982-11-01), Bate
patent: 4373248 (1983-02-01), McElroy
patent: 4377818 (1983-03-01), Kuo et al.
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4812898 (1989-03-01), Sumihiro
patent: 4855800 (1989-08-01), Esquivel et al.
patent: 4868619 (1989-09-01), Mukherjee et al.
patent: 4947222 (1980-08-01), Gill et al.
patent: 4949305 (1980-08-01), Toyama et al.

Affiliated with

Also associated with

Rating

Large-scale EPROM memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Large-scale EPROM memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Large-scale EPROM memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1652374