Schottky enhanced CMOS output circuit

Details Schottky enhanced CMOS output circuit Schottky enhanced CMOS output circuit

1989-02-23

1991-05-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 307451, 307585, H03K 19092, H03K 1900

Patent

active

050158899

ABSTRACT:
The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.

REFERENCES:
patent: 4023122 (1977-05-01), Oura
patent: 4578600 (1986-03-01), Magee
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 4791321 (1988-12-01), Tanaka et al.

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