Inverse transistor coupled memory cell

Details Inverse transistor coupled memory cell Inverse transistor coupled memory cell

1978-12-20

1981-03-17

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307303, 3072386, 357 35, 357 40, 357 43, H01L 2704, H03K 19082

Patent

active

042570590

ABSTRACT:
A semiconductor memory cell comprising first and second bipolar cell transistors cross-coupled by the inverse transistor action of third and fourth bipolar transistors. Each cross-coupling transistor is formed by a single emitter diffusion in an existing common base region of one cell transistor, above a common buried collector region of the same cell transistor. The use of cross-coupling transistors eliminates the need for a direct ohmic connection to the buried layer collector, thereby simplifying layout and reducing memory cell size.

REFERENCES:
patent: 4144586 (1979-03-01), U

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