Method of making a high performance MOS device having both P- an

Details Method of making a high performance MOS device having both P- an Method of making a high performance MOS device having both P- an

1988-09-09

1991-05-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 44, 437 57, H01L 21265

Patent

active

050155954

ABSTRACT:
A method for making an integrated circuit structure having both PMOS and NMOS devices with lightly doped (LDD) source and drain regions is disclosed utilizing a single photoresist mask in which a substrate is implanted with a low concentration dopant of a first conductivity type through a silicon nitride shielding layer. Spacers are then formed against the sidewalls of oxide and nitride coated polysilicon gate electrodes by RIE etching of a polysilicon layer formed over the nitride shielding layer subsequent to the first implantation. A separate photoresist mask layer is then formed over a portion of the structure and the remaining exposed portions of the shielding nitride layer are then etched, resulting in the formation of first el-shaped shielding members against the sides of the gate electrodes. The exposed polysilicon spacers are then removed and the substrate is implanted with a high concentration dopant of a second conductivity type at an energy level insufficient to penetrate through the el-shaped nitride spacer to form conventional source/drain regions in the substrate.

REFERENCES:
patent: 3996657 (1976-12-01), Simko et al.
patent: 3997367 (1976-12-01), Yau
patent: 4109371 (1978-08-01), Shibata et al.
patent: 4160683 (1979-07-01), Roche
patent: 4198250 (1980-04-01), Jecmen
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4209349 (1980-06-01), Ho et al.
patent: 4209350 (1980-06-01), Ho et al.
patent: 4234362 (1980-11-01), Riseman
patent: 4256514 (1981-03-01), Pogge
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4516316 (1985-05-01), Haskell
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4590663 (1986-05-01), Haken
patent: 4728617 (1988-03-01), Woo et al.
patent: 4729001 (1988-03-01), Haskell
patent: 4753898 (1988-06-01), Parrillo et al.
patent: 4764477 (1988-08-01), Chang et al.
patent: 4771014 (1988-09-01), Liou et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4843023 (1989-06-01), Chiu et al.
Barnes, John J. et al, "Short-Channel MOSFET's in the Punchthrough Current Mode", IEEE Transactions on Electron Devices, vol. ED-26, No. 4, Apr. 1979, pp. 446-453.
Bassous, E. et al., "Self-Aligned Polysilicon Gate MOSFET's With Tailored Source and Drain Profiles", IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, pp. 5146-5147.
Dennard, Robert H. et al, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions", IEEE Journal of Solid-State Circuits, vol. SC-9, No. 5, Oct. 1974, pp. 256-268.
Gaensslen, F. H., "Geometry Effects of Small MOSFET Devices", IBM Journal of Research and Development, vol. 23, No. 6, Nov. 1979, pp. 682-688.
Ghandhi, Sorab K., VLSI Fabrication Principles: Silicon and Gallium Arsenide, New York: John Wiley & Sons, 1983, pp. 424-427.
Ogura, Seiki, et al, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", IEEE Transactions on Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1359-1367.
Ohta, Kuniichi et al, "A Quadruply Self-Aligned MOS (QSA MOS) A New Short Channel High Speed High Density MOSFET for VLSI", IEDM, 1979, pp. 581-584.
Parrillo, L. C. et al; "A Versatile, High-Performance, Double-Level-Poly Double-Level-Metal, 1.2-Micron CMOS Technology", IEDM, 1986, pp. 244-247.
Pfiester, James R., "LDD MOSFET's Using Disposable Sidewall Spacer Technology", IEEE Electron Device Letters, vol. 9, No. 4, Apr. 1988, pp. 189-192.
Troutman, Ronald R., "VLSI Limitations from Drain-Induced Barrier Lowering", IEEE Transactions on Electron Devices, vol. ED-26, No. 4, Apr. 1979, pp. 461-469.
Tsang, Paul J. et al, "Fabrication of High-Performance LDDFET's With Oxide Sidewall-Spacer Technology", IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 590-596.
Wang, Paul P., "Double Boron Implant Short-Channel MOSFET", IEEE Transactions on Electron Devices, vol. ED-24, No. 3, pp. 196-204.

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