Process of making BiCMOS devices having closely spaced device re

Details Process of making BiCMOS devices having closely spaced device re Process of making BiCMOS devices having closely spaced device re

1988-10-24

1991-05-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 57, 437162, 437228, 357 43, 148DIG9, H01L 21328, H01L 21335

Patent

active

050155946

ABSTRACT:
A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.
In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact.
The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

REFERENCES:
patent: 4608589 (1986-08-01), Goth et al.
patent: 4686763 (1987-08-01), Thomas et al.
patent: 4735916 (1988-04-01), Homma et al.
patent: 4745087 (1988-05-01), Iranmanesh
patent: 4800171 (1989-01-01), Iranmanesh et al.
patent: 4808548 (1989-02-01), Thomas et al.
patent: 4824796 (1989-04-01), Chiu et al.
"A Self-Aligning Polysilicon Electrode Technology (SPEL) for Future LSIS", by Y. Misawa et al. (Hitachi Research Laboratory) IEEE 1987, pp. IEDM 87-33 through IEDM 87-35.

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