Semiconductor memory device having multibit data bus and redunda

Details Semiconductor memory device having multibit data bus and redunda Semiconductor memory device having multibit data bus and redunda

1999-06-03

2000-11-07

Nelms, David

Static information storage and retrieval

Interconnection arrangements

365212, 36523003, G11C 506

Patent

active

061445770

ABSTRACT:
Each global data bus is selectively connected via a connection circuit to any of local data buses associated with subarrays arranged on either side of the global data bus. Between row blocks is arranged a connection controlling circuit outputting a control signal which controls connection of the connection circuit. In each connection controlling circuit, a fuse corresponding to a location of a subarray including a defective memory cell is cut to provide column substitution without changing an order of global data buses.

REFERENCES:
patent: 5274593 (1993-12-01), Proebsting
patent: 5502675 (1996-03-01), Kohno et al.
patent: 5652725 (1997-07-01), Suma et al.
patent: 5930194 (1999-07-01), Yamagata et al.
"Ultra LSI Memory", by Kiyoo Ito, Advanced Electronics Series, Nov. 1994, pp. 166-175, 180-183 (with partial translations of pp. 168-169 and pp. 181-183).
"A Flexible Redundancy Technique for High-Density DRAM's", by Horiguchi, et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, pp. 12-17.

Affiliated with

Also associated with

Rating

Semiconductor memory device having multibit data bus and redunda does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having multibit data bus and redunda, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having multibit data bus and redunda will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1647925