Method and apparatus for implementing a serial memory architectu

Details Method and apparatus for implementing a serial memory architectu Method and apparatus for implementing a serial memory architectu

1998-08-19

2000-11-07

Nelms, David

Static information storage and retrieval

Interconnection arrangements

365 51, G11C 506

Patent

active

061445762

ABSTRACT:
A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.

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