Fast binary coded decimal incrementing circuit

Details Fast binary coded decimal incrementing circuit Fast binary coded decimal incrementing circuit

1979-03-02

1981-03-17

Thesz, Joseph M.

Registers

Platform operated

Platform actuated traffic counters

235 92SA, 2352BD, H03K 2700

Patent

active

042569540

ABSTRACT:
A Binary Coded Decimal (BCD) incrementing circuit and memory. The incrementing circuit has a small amount of delay associated with it so that it may be utilized as a stage of a shift register memory. The incrementing circuit includes an adder circuit, a sampling circuit and a detector circuit. The sampling circuit samples the most significant bit of a BCD digit when the least significant bit of the same digit is being outputted from the memory. The adder circuit adds one to the least significant bit in response to a control signal or one to the other bits in response to a carry condition in the adder and to a decimal carry signal. The detector circuit is coupled to the output of the memory, to the sampling circuit and to the control signal for generating the decimal carry signal and disabling the adder circuit when the control signal is present and the BCD digit being outputted is a decimal nine.

REFERENCES:
patent: 3324456 (1967-06-01), Brown et al.
patent: 3521036 (1970-07-01), Bartlett et al.
patent: 3798428 (1974-03-01), Izawa
patent: 3997765 (1976-12-01), Marathe

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