Integrated power-on-reset circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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H03L 700

Patent

active

061442380

ABSTRACT:
A circuit and a method are disclosed which offer a solution for integrating a power-on-reset circuit that is realizable in a small space, consumes very little power, and works for practically any rate of rise of the power supply. These goals have been achieved by detecting, in a first section of the circuit, when the supply voltage reaches the threshold voltage V.sub.TP of a p-channel transistor, and activates power-on-reset by forcing that signal to logical zero (active). This first section detects next when the supply voltage reaches 2V.sub.TP and signals to a second section of the circuit to start charging a capacitor. The charging rate of the capacitor is controlled in such a way that its voltage lags behind the supply voltage, so that if the rise of the supply voltage is very fast, the duration T.sub.D of power-on-reset is long enough to insure complete resetting of the circuits it serves, such as digital memory elements, digital registers etc. A third section of the circuit monitors the voltage of the capacitor and when this capacitor voltage has reached a certain predetermined percentage of the supply voltage, this third section terminates power-on-reset by switching that signal to logical one (inactive).

REFERENCES:
patent: 4697097 (1987-09-01), Rusznyak
patent: 5109163 (1992-04-01), Bebhamida
patent: 5172012 (1992-12-01), Ueda
patent: 5187389 (1993-02-01), Hall et al.
patent: 5300822 (1994-04-01), Sugahara et al.
patent: 5483187 (1996-01-01), Jang

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