Processing apparatus for data rate reduction

Details Processing apparatus for data rate reduction Processing apparatus for data rate reduction

1979-07-23

1982-03-16

Stewart, David L.

Multiplex communications

Wide area network

Packet switching

179 18FG, H04J 312

Patent

active

043205054

ABSTRACT:
A digital channel bank (11) has a plurality of channel units (17) interconnected to a digroup controller (10) over a shared data bus (30). A data processing circuit (FIG. 2) is included in each channel unit for the purpose of reducing the received signaling status information transmitted from each channel unit to the controller. The circuit (e.g., gates 24-27) serves to prevent single bit errors from being recognized as changes in the received signaling state. The circuit (gate 28) also insures that only changes in the signaling status, rather than current status, are reported to the controller. The circuit also incorporates a predetermined amount of delay for the purpose of eliminating multiple messages to the controller when the A and B path signaling bits change in adjacent signaling frames.

REFERENCES:
patent: 3166734 (1965-01-01), Helfrich
patent: 3420960 (1969-01-01), Jacoby
patent: 3629851 (1971-12-01), Werner
patent: 4059731 (1977-11-01), Green
patent: 4176256 (1979-11-01), Froth

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