Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1998-10-13
2000-11-07
Nguyen, Vinh P.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
324765, G01R 3128
Patent
active
061442143
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a current sensor circuit and, more particularly, to a Built In Current Sensor Circuit for use in quiescent power supply current, or IDDQ, testing of integrated circuits.
2. Description of the Background Art
Presently, there are several different types of testing methods for detecting defaults in integrated circuits. However, one particular method has been widely accepted and successful in the electronics industry. This one particular method comprises a complementary metal oxide semiconductor (CMOS) integrated circuit test method which is known as quiescent power supply current, or IDDQ, testing. IDDQ testing achieves high fault coverage and is used to detect physical defects in integrated circuits which are not detectable using logic or functional test methods. Although IDDQ testing has been used effectively on CMOS integrated circuits (ICs) with submicron feature sizes (integrated circuits utilizing dimensions less than 1 .mu.m), its effectiveness on ICs scaled to the deep submicron regime (typically L.sub.effective <0.5 .mu.m) has not been studied extensively.
As CMOS devices are scaled to the deep submicron regime, IC reliability can be reduced due to second order effects such as hot carriers and impact ionization. Although IDDQ testing is a potential test method for detecting leakage current in scaled ICs, the area overhead, the circuit performance, and the fault detectability penalties are particularly important in scaled ICs. These listed areas are the metrics which are used to evaluate the effectiveness of IDDQ testing along with fault diagnosability.
Testing very large scale integration (VLSI) and ultra large scale integration (ULSI) integrated circuits (ICs) is becoming increasingly more difficult, more time consuming, and more costly. This is due to increased circuit complexity and circuit densities, and reduced circuit feature sizes. Future VLSI/ULSI ICs will be tested using either existing, refined, or newly developed and more cost effective test methods and equipment. In addition, a greater emphasis must be placed on implementing design-for-test (DFT) strategies early in the design cycle due to the heavy burden and costs associated with back-of-the-line testing.
There are presently four types of tests performed on CMOS ICs for detecting and locating defects and faults. They are functional, logic, parametric, and IDDQ tests. The tests are performed in combinations at wafer-, bare-, die-, packaged-, assembly-, and system-levels. Functional IC tests are designed to verify whether the IC performs its intended function. Logic tests verify the logic operation of gates and registers, while AC and DC parametric tests are used to measure time-, voltage-, and current-varying parameters associated with the operational limits of the IC. Test parameters include propagation delay, operating current, and rise and fall time. Although IDDQ is actually a parametric test, it is considered unique due to its sensitivity to a specific class of physical defects to which CMOS ICs are susceptible.
IDDQ testing is performed by applying a predetermined set of test patterns to the primary inputs of a CMOS IC. The patterns, or vectors, are designed to force adjacent uncoupled nodes to opposite logic states. This creates a current leakage path from VDD to GND if the adjacent nodes become coupled through a short or bridge. A fault is detected by measuring the increased quiescent steady state current level at the VDD or VSS pins. The technique is effective since a broad class of physical defects is known to manifest itself as increased quiescent current levels easily observable using a sensitive current monitor. The technique also provides a high level of observability since it is unnecessary to propagate internal faults to output pins of the IC for observation. In addition, the number of test patterns required to provide high fault coverage in IDDQ testing is significantly fewer than those required for full functional and logic testing.
Alth
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Nguyen Vinh P.
University of South Florida
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